Logic Design, Circuit Design, Physical Verification, Industry-standard tools in semiconductor design, Physical Design, Design Methodologies, Rtl Design

power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

Tcl, Python, PERL, Seahawk, Tempus, primetime, Innovus, ICC2

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff

Docker, Python, AI ML background, Optimization, SOC domain, graph algorithms, combinatorial algorithms, geometry packages such as shapely

Fusion Compiler, IC Compiler, Cadence Genus, Block-level PnR, Physical Design, Innovus