Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification

Orchestration, C++, Data Structures, Data Security, Sql, Python

C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, functional and code coverage closure

Perl, Python, Tcl, ASIC design flow, LINT, Design Compiler, primetime, STA tools, UPF, Cadence Genus, RTL-to-gate-level synthesis, spyglass, CDC tools, CPF

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Questa tools, Axi, AMBA, Timing Constraints, ATPG, APB, microcontroller platforms, Cadence Virtuoso, AHB

Github, Sql, Shell scripting, Grafana, Ldap, Lsf, Tcl, Python, Perl, Jenkins, Gnu Make, Git, EDA Tools, Mentor Calibre, Synopsys VCS, Sungrid UGE, Cadence Virtuoso

C, Usb, Shell Scripting, Spi, Device Driver Development, Operating Systems, Gpio, I2c, Linux Kernel, Python, ADC, Wi-Fi, Embedded Systems