C, Perl, Verilog, Gdb, Python, Indago, SOC design, Cadence

Perl, System Verilog, Python, Tcl, primetime, Fusion Compiler, ICC2, Formality, LEC, UPF, Innovus, VHDL, EDA Tools, Synopsys Design Compiler, Linux Shell

Perl, C Programming, Python, Control Systems, active power management, silicon bring-up validation, power modeling, power thermal controllers, productization, Measurement

Cache, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, Dft, fabric coherence, DRAM, low-power design techniques