Ddr3, Spi, Uart, Usb, Logic Design, I2c, Pcie, AHB, Synthesis, formal verification, Custom SoC ASIC products, Static-timing closure, ddr2, Block-level function verification, Gate-level simulations, Micro-architecture, Rtl Design, UCL, Debug skills, CXL, D2D, Front-end design tools, Axi, Methodologies

Rcp, Rc, Tcl Scripting, Perl, low power design, Primepower, Sta, Constraints Signoff, DCG, PowerArtist, UPF, CPU micro-architecture, primetime, Synthesis, ASIC flow, Place and route tool understanding, DCT, CPF, high speed CPU implementation

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi