Logic Design, Front-end design tools and methodologies, Synthesis, Static-timing closure, formal verification, Debug skills, Block-level function verification, RTL coding techniques, Gate-level simulations, Timing signoff, Micro-architecture, Verification

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi