Matlab, Worst case identification, Process technologies, Monte Carlo analysis, Simulation verification, Block level topology selection, IC system partitioning, Physical layout management, AMs, Simulation on modern CAD tools, Analog Circuit Design, Architectural tradeoff analysis, Schematic generation, Routing tradeoffs, Spectre, Cadence tool set, Signal grounding, Top level simulation, Simplis, device physics, Post layout parasitic extraction, Die area optimization

cadence schematic capture , high-speed custom digital design flows, Hspice, AMs, Cadence Virtuoso, Spectre

Analog Circuit Design, Design Verification, Monte Carlo analysis, Modern CAD tools, Silicon validation and debug, Analog layouts, Simulation and Verification, Transistor level design flow, Schematic generation

Scripting, C, Verilog, Python, Amplifiers, Analog Circuits Design, Transistor level circuit design, Synopsys primesim, Cadence Virtuoso, EMIR flows, Reliability, Bias circuits

system integration, converter-level architecture, switching regulator circuits, DC-DC converters, Spectre, control-loop concepts, post-Silicon debug, analog mixed-signal IC design, extraction verification tools, design bring-up, Cadence Virtuoso, top-level analog simulations, high-voltage designs

bandgap references , PLLs, compensation techniques, ADC architectures, SERDES, capacitor matching, switched-cap circuits, Timing Analysis, noise analysis, top-level chip integration, Dft, high-speed TX feedback, silicon bring-up, operational amplifiers, transistor-level circuit design, Analog Mixed-Signal Design, LDOs, bias circuits, tapeout