Dac, Boost, ADC, ADE, Buck, PMIC building blocks, design-for-manufacturability practices, power management circuits, Analog Circuit Design, Spectre, reliability ESD considerations, Hspice, EDA Tools, waveform debug tooling, post-layout parasitics, Buck-Boost, LDO, mixed-signal IC design

Mixed-signal circuit design, PPA tradeoffs, Memory Cell Design, PLL clock-generation, Layout collaboration, Charge Pumps, Transistor-level design simulation, Clock buffers, Analog Design, Loop Filters

Monte Carlo analysis, Modern CAD tools, Design Verification, Simulation and Verification, Transistor level design flow, Analog layouts, Silicon validation and debug, Analog Circuit Design, Schematic generation

DFE, Duty Cycle Correction, BGR, Oscillators, High-speed clock distribution, Rx CDR, Tx Serializer Output Driver, CTLE, Generic Analog Circuits, Analog Circuit Design, EDA Tools, Bias Circuits, Deserializer, Circuit design simulation and analysis, LDO, Lower Nodes Experience, Amplifiers, VGA, Comparators, Power Management Circuits, High-Speed SerDes Tx and Rx blocks

Matlab, Analog Circuit Design, Monte Carlo analysis, Architectural tradeoff analysis, AMs, Spectre, Schematic generation and simulation, Physical layout management, Signal grounding and routing tradeoffs, Block level modelling, Block level topology selection, Post layout parasitic extraction, Die area optimization, Simplis, Top level verification, Simulation verification, IC system partitioning, Cadence tool set, Worst case identification

regulators , Verilog, Matlab, lab testing skills, IC design CAD tools, Bandgap bias circuits, TX, RX, Spice, ADCs, high-speed design techniques, Spectre, Pll, DACs, HSIM, Filters, deep sub-micron CMOS technologies