Perl, Python, formal verification, property checking, RTL integration, Uvm, systemverilog

Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, debugging firmware and RTL code, graphics pipeline knowledge, HLS tools, Simulation Tools, UVM testbenches, automating workflows, simulation profile efficiency improvement, TLM, UVM based verification frameworks

C, Makefile, Windows, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, debugging firmware and RTL code, graphics pipeline knowledge, HLS tools, Simulation Tools, UVM testbenches, automating workflows, simulation profile efficiency improvement, UVM based verification frameworks, TLM

Python, Perl, RTL integration, Uvm, formal verification, systemverilog, property checking

Systemc, Windows, Linux, Makefile, Shell, Verilog, Ruby, System Verilog, Perl, TLM, graphics pipeline knowledge, Simulation Tools, IP level ASIC verification, debugging firmware and RTL code, automating workflows, UVM testbenches, HLS tools, simulation profile efficiency improvement, UVM based verification frameworks

Tcl, Python, Perl, SV, SoC Verification, Uvm, Functional vectors generation, MBIST verification, SV UVM monitors, Test controller architecture, ATE Functional CHAZ vector enablement