static timing analysis, Synthesis, signal integrity analysis, pads log management, Place And Route, RDL routing, Floor Planning, EDA tools for physical design and verification, power grid design, full-chip physical design, Timing Closure, bump placement, Clock Tree Synthesis

Tcl, Python, processor designs, primetime, EDA Tools, Fusion Compiler, ICCompiler2, Innovus, lower node technologies, toplevel physical implementation

Tcl, Python, Processor designs, Toplevel physical implementation