Verilog, System Verilog, Assertion Checker Development, Coverage Closure, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, IP SOC Verification, Design Verification Failure Debugging

C, DDR, Perl, System Verilog, Python, Tcl, AMBA protocols, Uvm, Axi, HBM, APB, LPDDR, AHB

x86 assembly language , C, Perl, Ovm, Arm, Python, SVTB, CPU Architecture, Uvm, Power Management Verification

System Verilog, Building test benches from scratch, ASIC verification using UVM

Git, Confluence, Perl, Jira, Python, CPF, Uvm, UPF, systemverilog

Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm