Debugging of designs pre- and post-silicon, C, Shell, Verilog, System Verilog, interconnect, Microprocessor architecture, Testbench design and development using UVM methodology, Functional and code coverage, Directed and constrained random methodologies, Metric Driven Verification concepts, SoC Verification, Formal verification methodologies and assertions

Verilog, systemverilog, Digital and analog simulation tools, Uvm, PrimeSim, Verification strategy, Design Verification, Hspice, FineSim

redhawk , Tcl, Python, Perl, Pcie, Sta, Cadence Innovus, Physical Verification, EDA Tools, Calibre, high-speed interface IPs, floorplanning, CTS, Asic Physical Design, primetime, die-to-die D2D UCIe interconnects, Synopsys Fusion Compiler, IC Compiler, CXL, Voltus, EM analysis, PNR, SERDES