Dsp, System Verilog, Assembly level testcases, formal verification, Assertions, Digital Design, Uvm, Asic Design Verification, Processor Architecture, NPU, Debug, Gate-Level Simulation, Power aware verification

Unix, Shell, C, Perl, Linux, Verilog, Python, Uvm, systemverilog

Synopsys, Uvm, firmware interaction, AMs, Calibration, systemverilog, Mentor, Cadence, link training, Siemens, Register models, industry VIPs, Avery, SERDES