Makefile, Perl, automation, Python, Scripting, Tcl, ASIC design flow, advanced physical design methodologies, Synthesis, advanced process node challenges, AI ML-driven optimisation in physical design tools, modern EDA tools and flows, RTL integration, signoff, Place And Route, Physical Verification, power signal integrity, Floor Planning, power grid design, RTL-to-GDSII implementation, Timing Closure, hierarchical physical design strategies, Clock Tree Synthesis

redhawk , Static Timing Analysis, primetime, Quantus, Crosstalk Analysis, EM IR-Drop, Tempus, Cadence Innovus, Synopsys Fusion Compiler, LVS, Voltus, Calibre, Extraction, Physical Design, StarRC, EDA Tools, ERC, DRC, Antenna, PTSI

Nvme, Continuous Integration, Test automation, Pcie, Python Programming, Agile Development, Ocp, NAND flash operation, SSD firmware testing, Storage industry protocols, GIT development flow, Automated build, NVMe-MI

Java, Golang, Cassandra, Bash, HBase, Redis, Terraform, Kubernetes, Python, Airflow, Step Functions, GitOps, Cadence, Temporal, ArgoCD

regulators , Verilog, Matlab, deep sub-micron CMOS technologies, TX, IC design CAD tools, RX, high-speed design techniques, Spectre, DACs, Spice, Filters, lab testing skills, ADCs, HSIM, Bandgap bias circuits, Pll

regulators , receivers , Dac, Python Scripting, mixer, Oscillators, Temp Sensors, Transmitters, Pa, RF General, bandgaps, submicron CMOS technologies, RF modules, Dfm, parasitic reduction, linear switched ADC, VCO, Amplifiers, LNA, Cadence Virtuoso VXL, Mentor Calibre, Analog Mixed Signal Design, Esd, Analog Layout, Pll

Java, Devops, Code, Cursor, Kubernetes, Python, LangChain, Copilot, Claude, cloud-native technologies, knowledge graph solutions, CI CD, Codex, RAG GraphRAG, LLM and AI Agent architectures, LangGraph