Makefile, Systemc, Windows, Linux, Verilog, Ruby, System Verilog, Perl, graphics pipeline knowledge, Simulation Tools, IP level ASIC verification, debugging firmware and RTL code, automating workflows, HLS tools, UVM testbenches, TLM, UVM based verification frameworks, simulation profile efficiency improvement

C, Systemc, Windows, Linux, Makefile, Verilog, Ruby, System Verilog, Perl, debugging firmware and RTL code, graphics pipeline knowledge, Simulation Tools, IP level ASIC verification, automating workflows, UVM testbenches, HLS tools, TLM, UVM based verification frameworks, simulation profile efficiency improvement

Verilog, Unix Environment, General Logic Design concepts, Design verification experience

Noc, DDR, Shell, Pcie, Python, Usb, Perl, Ethernet, Tcl, subsystem integration verification, cdc, CHI, Uvm, constrained-random testing, coverage-driven verification, RDC, assertions, verification methodologies, Ace, lint flows, Emulation, systemverilog, FPGA prototyping, Axi, coverage and debug tools, APB, formal verification concepts, CXL, AHB, SVA, SoC fabrics

Perl, Pcie, Python, Tcl, SV, ONFI, MBIST, AI tools and Methodologies, Uvm, NAND, DFT architecture, LPDDR, Test controller architecture