bandwidth management , Microprocessor Cores, SystemVerilog Assertions, Specman E, Verification and debug of IP subsystem SoCs, Industry-standard simulators, Revision control systems, Constrained-random verification environments, systemverilog, Packet processing, Regression systems, Congestion control, Hierarchical memory subsystems, Full verification life cycle, Vector processing units

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

C, Python, Uvm, systemverilog