Noc, C, Perl, Verilog, Python, power analysis, Synthesis, processor design, low power design techniques, arithmetic units, SoC designs, memory hierarchies, design of IPs and Subsystems, systemverilog, integration flows, Asic Design Verification, Fabrics, accelerators, micro-architecture, bus architectures

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

Verification methodology., Soc, IP design verification, ASIC Design, Functional coverage, systemverilog, Rtl Design