Ovm, Python, Perl, power management techniques, Uvm, verification methodologies, Timing Analysis, systemverilog, digital hardware design, static design checks, cdc, Linting, Verilog Hdl, design specifications, physical implementation, Synthesis, Dft, RDC, X-Propagation

AMBA protocols - AXI AHB APB, Verilog, LINT, cdc, ECO fixes, Logic design RTL coding, Asynchronous interface, Synthesis, formal verification, SoC clocking reset architecture, SoC design and integration, Multi Clock designs, System-Verilog

telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts

Verilog, Pcie, Low power estimation, Low power RTL design, Microarchitecture synthesis, LINT, Timing Closure, Rtl Design, CXL, cdc