Tcl, Python, Fusion Compiler, processor designs, primetime, EDA Tools, ICCompiler2, Innovus, lower node technologies, toplevel physical implementation

Tcl, Python, lower node technologies, processor designs, Fusion compiler, primetime, EDA Tools, ICCompiler2, Innovus, toplevel physical implementation

static timing analysis, signal integrity analysis, full-chip physical design, pads log management, Floor Planning, RDL routing, Place And Route, bump placement, EDA Tools, Synthesis, power grid design, Timing Closure, Clock Tree Synthesis