ORD - Open Roads Design, Junctions, Highway related BIM exposure, Autocad, Civil 3D, Quality process procedures implementation, highway rehab related design, Microstation, Modelling, traffic management plans, CDE awareness, Road Signs Markings

Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation

Machine Learning, Distributed Systems, Tensorflow, Pytorch, Predictive Analytics, Python, Big Data, Clustering, Deep Learning, MLops, Spark, GenAI, Telemetry Analytics, Data Pipelines, Random Forests, MLflow, Vector Databases, Time-Series Forecasting, AIOps, LLMs, Production AI Systems, anomaly detection, Cloud Data Architecture, Statistical Modeling

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

Python Scripting, Cadence Innovus, Physical design signoff, ECO implementation, EMIR analysis

high-performance datapath architecture, ASIC SoC architecture, congestion control, Traffic Management, SystemVerilog RTL design, advanced networking architectures, infiniband, collective communication acceleration, 1.6T Ethernet systems, AI HPC interconnects, RDMA packet processing, High-speed SerDes, UCIe, reliability mechanisms, PCIe Gen6, Ultra Ethernet, full ASIC lifecycle, RoCEv2, CXL, Ethernet Scale-Up Networking

Python, Rtos, Linux, Embedded software architecture, C/C++, AI development environments

Automation Frameworks, Perl, Python, Tcl, AI-native automated methodologies, Methodology, Physical Design, Sub-3nm device physics