Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Test Plan Creation, Verilog, Execution, DV environments, cdc, APB bus protocols, block functional models, BFM, Uvm, UPF, systemverilog, formal verification methodologies, VHDL, RDC, constrained random verification techniques, CPF, AHB

test environments , Test Cases, System Verilog, Test Planning, low-power design verification, verification test benches

python, perl, System Verilog, Computer Architecture, Network on Chip verification, Configurable IP verification, coherency architecture, AMBA protocols, VIP integration, coherent protocols, bridge checkers, protocol checkers

code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage

Automation Frameworks, Ovm, Cadence Palladium, Mentor Veloce, verification methodologies, emulation tools, emulation platforms, Uvm

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB