Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, UVM methodology, Microelectronics, Questa, Electrical Engineering, Test generators toolkits for ARM CPU validation, Testbench development

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification

Verilog, Matlab, Python, FPGA-based emulation, DSP concepts

Perl, Python, Synopsys VCS, Cadence Xcelium, Uvm, systemverilog