Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug

Jtag, Perl, Verilog, System Verilog, Python, Tcl, Mentor Questa, Cadence Xcelium, Mixed Signal Verification, Uvm, Synopsys VCS, APB, CRI, IJTAG

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

Verilog, System Verilog, VHDL, Xcelium, Questa, Simulator exposure with VCS, Proficient in simulation and HW languages, Uvm, UVVM