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Role Summary

We are looking for an experienced Sr. Principal Analog Design Engineer to drive the design and delivery of highspeed interface IPs, with a strong emphasis on DietoDie (D2D) interconnects based on the UCIe standard and advanced package technologies. The role requires handson ownership from architecture through silicon bringup, working closely with layout, verification, package, and system teams.

Key Responsibilities

Architect, design, and deliver highspeed analog / mixedsignal circuits for DietoDie and chipletbased systems, including UCIecompliant interfaces.
Own analog blocks for highspeed interfaces such as clocking, TX/RX frontends, termination schemes, biasing, and equalization support circuits.
Drive architecture definition, feasibility analysis, and design tradeoffs considering signal integrity, power, noise, and packaging parasitics.
Perform schematic design, simulation, and optimization across PVT corners using industrystandard EDA tools.
Work closely with advanced package teams (2.5D / 3D, interposers, organic substrates) to cooptimize circuit and package design.
Support layout reviews, parasitic extraction analysis, and postlayout signoff for highspeed performance.
Collaborate with AMS verification, digital, and system teams to enable fullchip integration and validation.
Participate in silicon bringup, debug, and characterization, including correlation with simulation results.
Contribute to design methodology, checklists, and best practices for highspeed analog and D2D designs.

Required Qualifications

Bachelor's or Master's degree in Electrical / Electronics Engineering or related field.
12+ years of handson experience in analog / mixedsignal IC design.
Strong experience with highspeed interface design (e.g., DDR, PCIe, SerDes, DietoDie links).
Solid understanding of UCIe standard concepts, D2D PHY requirements, and chiplet architectures.
Experience working with advanced packaging technologies and understanding packageinduced effects on highspeed signaling.
Proficiency in schematiclevel design, simulation, and debug across PVT corners.
Strong fundamentals in analog circuit theory, signal integrity, noise analysis, and clocking.

Preferred / NicetoHave Skills

Direct handson experience with UCIe PHY design or integration.
Exposure to AMS verification flows and mixedsignal simulation environments.
Experience with postsilicon debug and correlation.
Knowledge of power integrity, thermal considerations, and packageaware design flows.
Ability to mentor junior engineers and lead technical discussions.

What Success Looks Like

Robust, scalable UCIe / D2D analog IPs meeting performance, power, and reliability targets.
Smooth collaboration across design, verification, and packaging teams.
Predictable execution aligned with project milestones and KPIs / OKRs.
Strong ownership mindset from architecture to silicon.

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Sr. Principal Design Engineer