Usb, Perl, Verilog, Sata, Python, DV methodologies, PCI Express, Uvm, systemverilog, VMM, constrained random verification, functional coverage

Ovm, Perl scripting, Verilog, Post-silicon bring-up HW-SW debug, AXI protocol, DDR PHY architecture, Uvm, JEDEC standards, systemverilog, DFI protocol, LPDDR4, debug and root-cause skills, SS SoC post-silicon issues, AHB, LPDDR5

C, Debugging, Soc Architecture, Perl, Verilog, Python, CPU architecture, AMBA protocols, systemverilog, Emulation, Simulation, Verification fundamentals, Assembly