Position Overview

We are looking for a Lead Engineer in SoC Verification to join our team and contribute to the Formal Property Verification (FPV) and Connectivity Verification of complex SoC designs.

The engineer will be responsible for developing, executing, and maintaining formal verification strategies to ensure exhaustive property coverage, structural correctness, and architectural compliance across critical blocks and subsystems.

This role requires strong expertise in formal methodologies, hands-on experience with industry-standard formal tools, and the ability to collaborate closely with RTL design, architecture, and full-chip verification teams to ensure first-pass silicon success. The position aligns with core verification competencies expected within the organization for mid-senior technical roles.

Key Responsibilities

Formal Property Verification (FPV) Ownership

Develop, implement, and execute block-level and subsystem-level formal verification plans.
Write, qualify, and maintain SystemVerilog Assertions (SVAs) and formal properties ensuring full functional intent is captured.
Drive property convergence, coverage closure, and modeling of constraints and abstractions needed for formal completeness.
Analyze unreachable or failing properties and work with design and architecture teams to refine specifications or fix design issues.

Connectivity and Structural Verification

Own connectivity verification Complex SoC, ensuring structural correctness of interconnects, control paths, resets, clocks, interrupt lines, and memory maps.
Validate structural rules, detect connectivity mismatches, and ensure alignment with architectural specs.

Collaboration With RTL, Architecture & Full-Chip Verification Teams

Partner with RTL designers and SoC architects to understand design intent, microarchitecture, and corner-case requirements.
Support integration teams with structural checks, static rule validation, and early bug discovery.
Provide clear documentation of formal verification results, coverage status, and sign-off readiness.

Debug & Issue Resolution

Debug complex failures using waveforms, formal counterexamples, and design traces.
Collaborate cross-functionally to resolve property failures, unreachable states, and integration mismatches.
Provide actionable insights to design teams for specification alignment and design correction.

Tool, Infrastructure & Automation

Work with formal verification tools (JasperGold, VC Formal, Questa PropCheck, etc.) to run proofs, coverage, and abstraction flows.
Build or enhance formal verification infrastructure, scripts, checkers, libraries, and connectivity test frameworks.
Use scripting languages (Python, Perl, TCL) to improve automation and efficiency.

Documentation & Technical Communication

Prepare detailed reports on FPV status, property coverage, connectivity results, and sign-off compliance.
Communicate verification risks, gaps, and progress clearly to project leadership and cross-functional teams.

Qualifications

Bachelor's or master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
7–10 years of experience in SoC or IP verification with at least 3–5 years in formal property verification.
Strong proficiency in SystemVerilog, Assertions (SVA), and formal verification methodologies.
Experience with leading formal tools such as Cadence JasperGold, Synopsys VC Formal, Mentor/Siemens Questa Formal.
Strong understanding of SoC architecture, interconnects (AXI/AHB), resets, clocks, memory maps, and peripheral interfaces.
Experience with connectivity verification flows and static structural analysis.
Solid debug skills with the ability to interpret counterexamples, waveforms, and design behavior.
Proficiency in scripting (Python, Perl, TCL) for automation and productivity.
Strong communication skills with the ability to collaborate effectively across design, architecture, and verification teams.

Preferred Qualifications

Experience with formal apps such as Connectivity, X-Propagation, Security, Reset, CDC/RDC formal checks.
Knowledge of block-level and subsystem-level functional verification methodologies (UVM/OVM) to complement formal flows.
Familiarity with low-power architecture (UPF) and power-aware formal checks.
Exposure to static verification tools for lint, CDC, RDC, and structural rule checking.

Why Join Us

Opportunity to lead formal verification sign-off for a strategic SoC program.
Work closely with top engineers in design, architecture, and full-chip verification.
Access to advanced formal and connectivity verification infrastructures.
Collaborative, innovative, and quality-focused engineering environment.
Strong career development and cross-functional growth opportunities.

About Us

L&T Semiconductor Technologies is a leader in innovative semiconductor solutions, committed to pushing the boundaries of technology to create a smarter, more connected world. We are an equal-opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees

Senior Formal Verification Engineer

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