General Summary:

Qualcomm is a world leader in wireless technologies and a driving force behind the connected world of the future. As a Senior RTL Design Engineer, you will be at the core of Qualcomm's SoC development efforts, working on high-performance, power-efficient, and scalable logic designs for next-generation wireless and computing solutions.

You will contribute to defining and implementing complex digital designs that are integral to Qualcomm's industry-leading SoCs. This role offers the opportunity to work with some of the brightest minds in the industry, pushing the envelope on performance, power, and silicon complexity.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field and 6+ years of hardware engineering experience
OR
Master's degree and 5+ years of experience
OR
PhD and 4+ years of experience

Required Skills & Experience:

12+ years of experience in RTL design, micro-architecture, and logic design for large-scale SoCs
Hands-on expertise in Verilog/SystemVerilog for design and simulation
Proven track record in SoC architecture, integration, and synthesis
Strong working knowledge of:
AMBA protocols (AXI, AHB, APB)
Clocking/reset/debug architectures
Common SoC peripherals (USB, PCIe, SDCC)
Experience in low-power SoC design, including multi-voltage and power domain handling
Hands-on with multi-clock domain design, asynchronous interfaces, and related challenges
Experience with synthesis tools such as:
Synopsys Design Compiler
Cadence Genus
Synopsys Fusion Compiler
Deep understanding of timing analysis and STA concepts
Familiar with PrimeTime or equivalent tools
Exposure to constraint development, timing closure, and design convergence
Strong collaboration skills to work with DFT, PD, and STA teams during integration and signoff

Preferred Qualifications:

Experience in low-power techniques like power gating, clock gating, and multi-mode/multi-corner (MMMC) analysis
Understanding of DFT concepts and how RTL decisions impact testability
Prior experience in developing reusable design components or IPs
Familiarity with version control and design flow automation using scripting (TCL, Python, Perl)

Principal Duties and Responsibilities:

Define, implement, and verify micro-architecture for new features within Qualcomm SoCs
Develop high-quality, reusable, synthesizable RTL code using Verilog/SystemVerilog
Collaborate with cross-functional teams (DFT, PD, STA, Architecture) to ensure timing, functionality, and power goals
Drive synthesis and timing convergence activities through the full lifecycle of SoC development
Perform debug and root cause analysis for functional and timing issues
Contribute to the improvement of design flows, methodologies, and best practices
Review and maintain technical documentation, design specifications, and timing constraints

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