Dsp, System Verilog, Gate-Level Simulation, Power aware verification, Assembly level testcases, Uvm, Assertions, Asic Design Verification, NPU, Processor Architecture, Debug, formal verification, Digital Design

IP SoC verification, ASIC-SoC design verification, systemverilog

Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

Unix, Shell, C, Perl, Linux, Verilog, Python, Uvm, systemverilog

C, Python, Uvm, systemverilog

Scala, Python, System Verilog, Chisel, Uvm