Rtl Design, SDR architectures on FPGA, logic analyzers, DDR interfaces, high-speed DSP pipelines, DMA engines, digital communication systems, AXI infrastructure, spectrum analyzers

Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations