redhawk , Shell, Python, Tcl, SC CADENCE, semiconductor device physics, Voltus, Calibre, EDA Tools, EMIR tool flows, Reliability verification, SVRF, ESD PERC design rules

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff

layout verification , automation, Mentor Graphic Calibre DRC, AI tools, Layout Design, skill coding, Cadence VLE

UNIX, Perl, System Verilog, Python, Tcl, primetime, Fusion Compiler, ICC2, Formality, UPF, Innovus, VHDL, EDA Tools, Synopsys Design Compiler, Linux Shell, low-power design techniques

strace , Github, Golang, Machine Learning, C, CSS, Gdb, PostgreSQL, Bash, Dns, HTML, Smtp, Javascript, Linux, Perl, PERL, MySQL, Tls, Python, AJAX, Ai, AI APIs, Large Language Models

Pvs, Tcl, Python, Perl, LVS, Xl, Analog layout design, DRC, Calibre, R3D, PEX, virtuoso

Fusion Compiler, IC Compiler, Cadence Genus, Block-level PnR, Physical Design, Innovus