Unix, Shell, Pcie, Linux, System Verilog, Constraint based Random verification, Coverage strategies and measurement, Skill, Test cases coding, Uvm, Digital Design and Verification methodologies, Python Script, DDR verification, VIP coding, Test Plan design

C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

C, C++, Makefile, Windows, Soc Architecture, Linux, Perl, Verilog, Python, Systemc, HLS tools, ASIC Design Flow, UVM testbenches, Asic Design Verification

System Verilog, TLBs, Store buffer, Memory consistency models, Speculative loads, Physical register files, Flush replay, Debug tools, MMU, Cache hierarchy, Instruction fetch, Page table walkers, Interrupt handling, Register mapping, Protection, Uvm, LR SC, Reorder buffer, Bypass networks, Scheduler, Stores, Atomics, Coherence protocols, Decode rename, Issue queue

Verilog, Ovm, System Verilog, Synopsys VCS, Cadence IES, VMM, formal property checking tools, Uvm