C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

Synthesis, RTL code in Verilog, SoC integration, Timing Closure, RTL logic design, micro-architecture specifications, Verification, timing optimization, assertions coverage analysis

Vcs, Gdb, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

rtl development , Verilog/SystemVerilog, ASIC methodology, Microarchitecture, ARM-based SoCs

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

ASIC IP Design, SystemVerilog Assertions, systemverilog

Hard IP integration, Clock and Power distribution, STA setup convergence methodology, Power Integrity Analysis, Hierarchical design implementation, Automation scripts within STA tools, Timing Closure, Timing ECO Implementation, Floor Planning, Debugging skills in implementation issues, ASIC Physical implementation, Global signal planning, Physical convergence, Tweaker Primetime based ECO flows