Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC

C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

Verilog, Python, Perl, Vcs, Gdb, bring-up lab debug, Debussy, ASIC design flow, floor-planning, Timing Analysis, Eco, Rtl Design

Synthesis, micro-architecture specifications, Timing Closure, SoC integration, RTL code in Verilog, Verification, RTL logic design, timing optimization, assertions coverage analysis

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

Static timing analysis, Linux, Lsf, Bitbucket, Git, Unix, Splunk, AI ML, Python, Jenkins, EDA Tools, convolutional Networks, make, GenAI, SW development, CI CD process, Implementation, design layout constraints, DesignSync, debug tools, Power-aware flows, UPF, Clocks, Design Verification, cdc, reinforcement learning, Graph Neural Networks, SDC, Dft, RDC

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis