Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Synthesis, micro-architecture specifications, Timing Closure, SoC integration, RTL code in Verilog, Verification, RTL logic design, timing optimization, assertions coverage analysis

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

Shell, C, Perl, Verilog, Python, Tcl, EDA Tools, UVM methodology, systemverilog