Job Role: Memory Layout Design Engineer (2 – 10 years exp.)

Role: Execute Layout Design of SRAM/CAM/RF compiler memories 3nm and lower technology.Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories. Should possess good knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes.

Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required.

Behavioral Traits: Ability to follow established procedures and work in a distributed team environment. Work independently to deliver high quality results on time.19:T7f0,Job Description:

Job Requirements:

Minimum 3 years of experience with strong layout knowledge.
Bachelor's degree required.
Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).
Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description:

Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
Manage scheduling, timelines, and layout floor-planning.
Responsible for start-to-end deliverables with quality within the planned schedule.
Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.

Skill Set (Memory):