Pcie, Verilog, Ethernet, Prototyping, Python, Scripting, Tcl, UCIe chiplet interconnects, AI tools, cdc, area optimization, Emulation, systemverilog, high-speed IO protocols, Rtl Design, formal verification, RDC, LINT, Timing Closure, silicon bring-up, CXL, micro-architecture, power efficiency

Distributed Systems, Kubernetes, Python, Infrastructure automation, GPU resource management, Resource scheduling, Go, Performance optimization, Container runtimes, Multi-tenant platform architecture

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Golang, Django, React, Azure Functions, Terraform, Docker, Ansible, FastAPI, Kubernetes, Python, Container Apps, Log Analytics, Bicep, Application Insights, Azure Monitor

System Verilog, formal verification methodologies, C testcases, scripting for flow integration, Uvm, AI ML-driven EDA tools

Software configuration management, Python Programming, Low-level device drivers, Static analysis tools

python, Microstation, highway and development infrastructure design, pavement alignment, digital workflows automation, Bentley ORD, drainage utilities, Civil cell