Usb, Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Tcl, Xcelium, Design Verification, QuestaSim, Uvm, systemverilog, Riviera, Axi, MIPI, APB, CXL, AHB, SoC Verification

Perl, Verilog, Computer Architecture, Oops Concepts, Python, VMM, UVM methodology, constrained random verification, systemverilog, functional coverage

Perl, Vcs, Python, Tcl, Verdi, Xcelium, ARM CPU Subsystem CPUSS verification, Uvm, systemverilog, AMBA CHI coherency and interconnect protocols

SV, PSS, Uvm

C, Verilog, Ovm, Perl scripting, Python, System Verilog, VMM, Axi, Uvm, AHB

Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, verification concepts, simulation logs, Uvm, ASIC SoC functional verification, waveform tools, constrained-random stimulus, BUS Protocols, assertions, SVA, functional coverage