Verilog, Pcie, SVA, formal verification, Assertions, Uvm, interconnect protocols, debugging complex RTL, systemverilog, CHI, AHB, Functional verification methodologies, Axi, testbench issues, Coverage

Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, Xcelium, Design Verification, QuestaSim, Uvm, systemverilog, Riviera, MIPI, Axi, APB, CXL, AHB, SoC Verification

Verilog, Sata, Python, Perl, Usb, VMM, constrained random verification, Uvm, functional coverage, PCI Express, systemverilog, DV methodologies