Phase Interpolator, CAD tools for circuit simulation, Cadence tool experience, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Vcs, Perl, Verilog, System Verilog, Python, Tcl, LINT, cdc, Xcelium, spyglass, RDC, Questa, Questa CDC

power integrity , DDR, Pcie, Usb, Ethernet, board-level debugging, Reliability Testing, Pcb Design, Dfm, embedded computing system boards, reliability compliance, Dft, Safety, power delivery networks, embedded board bring-up validation, storage management interfaces, BOM risk assessments, component selection, timing requirements, high-speed PCB layout, Signal Integrity, Failure Analysis, quality requirements, schematic capture, design changes

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2

Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB

boundary scan , Perl, Scripting Languages, Python, Tcl, scan compression, JTAG IEEE 1149.1, Scan Insertion, memory BIST, DFT methodologies, DFT EDA tools, test pattern generation, ATPG, silicon bring-up, post-silicon debug, Cadence Modus Genus