STA tools - Tempus, Static Timing Analysis, Spice to STA correlation, Physical Verification DRC LVS DFM, primetime, Placement of hard macros, Clock-tree synthesis, Routing timing optimizations, Hierarchical designs, Floorplan design, Low Power implementation, Parasitic Extraction, Congestion reduction techniques, Timing analysis validation and debug, PCIe timing closure

Static Timing Analysis, Clock Tree analysis, primetime, POCV margin methodology, Fishtail, IO budgeting, Tempus