Job Description

We are seeking a diligent Verification leader to join our team at Renesas. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely.

Responsibilities:

Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors.
Work closely with system architects to understand high level specifications to be able to verify them.
Work with various EDA vendors to deploy next generation tools
Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones
Promote continuous improvement to design techniques to ensure Zero Defect chips
Collaborate with SME's and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies
Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations
Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs.
Drive best in class verification methodologies collaborating with global internal and external SME's and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI

Qualifications

Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science
At least 10+ years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.
Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
Experience in Microcontroller and Microprocessor architecture & Interconnect
Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers.
Advanced knowledge of Verilog, System Verilog, C/C++, Shell.
Good knowledge in scripting like Perl, TCL or Python is a plus
High proficiency in Metric Driven Verification concepts, functional and code coverage.
Expertise in directed and constrained random methodologies.
Good knowledge of formal verification methodologies and assertions.
Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
Excellent written and verbal communication skill.
Must have worked on complex, multi-core SoC's with extensive interconnects and a large range of peripherals.
Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.

You can apply on below links also:

Sr Staff DV- https://smrtr.io/pZnD9

Principal Eng, DV - https://smrtr.io/pZnDf

Sr Staff/ Principal Engineer- Design Verification