Matlab, Worst case identification, Process technologies, Monte Carlo analysis, Simulation verification, Block level topology selection, IC system partitioning, Physical layout management, AMs, Simulation on modern CAD tools, Analog Circuit Design, Architectural tradeoff analysis, Schematic generation, Routing tradeoffs, Spectre, Cadence tool set, Signal grounding, Top level simulation, Simplis, device physics, Post layout parasitic extraction, Die area optimization

High-Speed ADC Design, Analog IC Design, Mixed-Signal IC Design, Cadence Virtuoso

UNIX, signals systems and transforms, AC DC analysis, circuit simulation tools, MOS transistors, High Volume Manufacturing, feedback systems, end-to-end design flow, poles zeros compensation, layout tradeoffs, Analog Circuit Design, Mixed Signal Design, Modeling Tools, layout verification tools, CMOS Bi-CMOS fabrication processes, loop dynamics, device physics

synopsys tools , Analog Circuit Design, Mentor Siemens Calibre, Physical Verification, ERC, DRC, Custom Layout, LVS, Cadence Virtuoso, Analog Layout Design

temperature sensors , Analog IP design, High Voltage charge pumps, Silicon Characterization, Oscillators, ADCs, Probing, Current and Voltage reference, Switch capacitor circuits, EDA Tools, LDO, Voltage regulators

Scripting, C, Verilog, Python, Amplifiers, Analog Circuits Design, Transistor level circuit design, Synopsys primesim, Cadence Virtuoso, EMIR flows, Reliability, Bias circuits

Perl, Python, Tcl, CMOS Analog Circuit Design, StarRC, Calibre xRC, Assembler, ADE XL, Cadence Virtuoso, Spectre