Spi, I2c, Uart, Can, Ethernet, functional safety, post-silicon verification, AMS CDC digital verification, UPF based verification, Uvm, GLS, formal verification, CSI, DV firmware verification, Specman, systemverilog, Axi, APB, AI ML based DV, cybersecurity processes, PAGLS, CPF, C-based SoC design verification, AHB

Perl, Python, Test plan development, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, Transaction level modelling, systemverilog, DSP instruction set architectures, Industry standard I/O interfaces, Object-oriented design, AMBA bus protocols, RTL development environments, Baremetal processor environments, Verification methodologies, FPGA and emulation platform knowledge, Formal verification methods, UPF based low power verification, Hardware description languages

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, test bench infrastructure, transaction level modelling, verification platforms, formal verification methods, emulation platforms

Perl, Python, Fpga, Uvm, systemverilog, RTL development environments, Test plan development, Low power verification methods, Emulation platforms, Transaction level modelling, DSP instruction set architectures, AMBA bus protocols, Baremetal processor environments, Verification methodologies, Formal verification methods, Coverage measures, Hardware description languages

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, verification platforms, transaction level modelling, test bench infrastructure, formal verification methods, emulation platforms

DDR, Pcie, SV, HBM, Design Verification, CXL, UCIe, Uvm

Verilog, systemverilog, Rtl Design, Verification Manager, Test Bench