Soc, Bash, Perl, Python, Tcl, Siemens Calibre, Cadence Pegasus, Tempus, Cadence Innovus, Cadence Voltus, Cadence Genus, ASIC, Ansys RedHawk, Physical Design, GDSII

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis