rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, STA timing closure, ERC, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

altium , board layout , Uart, Orcad, Jtag, Shell, Perl, Python, SWD, ALLEGRO, high-speed interface characterization, Logic Analyzer, source meters, multimeters, BOMs, thermal cameras, spectrum analyzers, Schematics, Oscilloscope, PCB-level debugging

Uart, Spi, Perl, Verilog, I2c, Python, Tcl, Synthesis, cdc, Timing Analysis, AMBA protocols, digital IP development, systemverilog, Rtl Design, RDC, EDA Tools, DMA, low-power design concepts

Perl, Python, Tcl, constraint generation, Clock Tree Implementation Techniques, Rtl Design, Synthesis, STA using Primetime, Physical Verification, UPF CPF definition, Timing Closure, Power Estimation, ASIC Design, Low Power Power Analysis, Validation, formal verification, Place and Route Implementation

S3, Kafka, Rabbitmq, Devops, Lambda, Docker, ECS, Sqs, Flask, FastAPI, Python, AWS, Step Functions, CI CD, AsyncIO, EKS, SageMaker, Fargate, ECR, infrastructure-as-code