ASIC physical implementation, RTL to GDSII design flow, Timing constraints and sign-off, Scripting in Perl/Tcl/Python, Fusion Compiler

stylus , Tcl Scripting, UPF development, Conformal VCLP, Synopsys Fusion Compiler, Cadence Genus, RTL synthesis, Physical Design, LEC closure, VCLP analysis

power optimization , Physical Design Verification, Place-and-Route Tools, Timing Closure, Sub-5nm Technology Enablement, TCL/Perl Scripting