C, Debugging, System Verilog, Python, Architecture, IP Quality Control, low power design, Synthesis, Timing Analysis, Behavioral Coding, Design Automation, Digital Design, Rtl Design, Verification Test Cases

Pcie, System Verilog, RTL coding Verilog, AMBA controller IP, CXL, FPGAs

Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design

clocking , Svn, DDR, Git, Perl, Verilog, Python, Tcl, Synthesis, cdc, CHI, Ace, AMBA protocols, systemverilog, Rtl Design, RDC, HBM, LINT, EDA Tools, Resets, performance optimization, LPDDR

Pcie, Verilog, Ethernet, Debugging, Scripting, Python, Tcl, UCIe chiplet interconnects, digital design fundamentals, high-speed IO protocols, systemverilog, Rtl Design, CXL, micro-architecture, low-power design techniques

Perl, Verilog, Python, Synthesis, processor design, low power design techniques, arithmetic units, Chisel, memory hierarchies, design for testing, timing power analysis, systemverilog, Asic Design Verification, accelerators, micro-architecture, bus architectures

FPGA-SoC interfacing, Python Perl, Peripheral interfaces SPI I2C UART DDR4, Xilinx FPGA design and prototyping, AMBA protocols AXI AHB APB, Protocol analyzers SPI CAN Ethernet, Hardware debugging tools Oscilloscope Logic Analyzer, Micro-architecture definition and logic design, Implementation of DSP algorithms on FPGA Radar EW systems, RTL Design using Verilog VHDL, Constraints development linting CDC analysis, Simulation and verification methodologies, FPGA synthesis implementation and timing closure, High-speed interfaces PCIe Ethernet JESD204B C