Digital Logic Design, synchronization techniques, multi-clock domain designs, Memory Architecture, Verilog RTL coding, high-performance memory subsystems, high-speed serial interfaces, ASIC design methodologies, micro-architecture development

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

Vcs, Verilog, Gdb, ASIC design flow, Rtl Design, floor-planning, Eco, Timing Analysis, Debussy, bring-up lab debug

rtl development , Usb, Pcie, Ethernet, AI tools, UFS, HSIO standards, micro-architecture

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification