C, Verilog, System Verilog, IP level ASIC verification, Writing and debugging testbenches, Debugging SOC IO interfaces with Transactor solutions, SOC design model build experience, Debugging firmware and RTL code using simulation tools, Understanding of PCIe USB Ethernet standards, Hands-on experience on Zebu Palladium Veloce platform, BIOS OS bring up on full X86 SOC emulation platform

Gpu, C, Cpu, Usb, BIOS, Makefile, Verilog, Ruby, System Verilog, Pcie, Perl, Transactor solutions, Memory subsystem, Ethernet standards, Debugging firmware, Test Architecture, Emulation Methodologies, Zebu, SOC Design Model, Testbenches, Palladium, Asic verification, RTL code, Veloce