About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As an Analog Layout Staff Engineer with Marvell, We are building next-generation 50G/100G optical link solutions for data-centric computing, leveraging advanced silicon photonics integrated with cutting-edge CMOS electronics. We're looking for a highly skilled AMS Layout Design Engineer to architect and implement high-speed analog and mixed-signal circuits for our photonic transceivers and electronic ICs (EICs).

You'll work closely with our Analog and Mixed Signal (AMS) team to deliver scalable, low-power, high-performance EICs in leading edge technology processes for optical compute and interconnects.

What You Can Expect

Working with global teams across Cannada, the U.S., and INDIA, you will do layouts and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively until the design meets specifications. Project durations vary from a few months to a year and a half with flexibility to switch based on changing priorities is appreciated.
To be successful in this role, you must:
Have fundamental understanding of electrical concepts, likely acquired through a degree in Electrical Engineering (graduate or undergraduate).
Design the physical layout of high-speed SERDES circuits in FinFET technologies (5nm and below), including TX, RX, PLL, CDR, and equalization blocks.
Own and drive the floor planning, transistor-level layout, and full custom mask design of analog, mixed-signal, and high-speed digital blocks.
Collaborate closely with circuit design teams to understand schematic requirements, optimize layout for performance, area, and power, and ensure first-pass silicon success.
Perform advanced layout techniques for signal integrity, device matching, and low-noise design in high-speed and high-density environments.
Execute parasitic extraction (PEX) and work with circuit designers for layout-versus-schematic (LVS), DRC closure, and post-layout simulation and optimization.
Apply strong understanding of ESD, latch-up, and reliability considerations to layout design practices.
Maintain schedule ownership of layout milestones, working with program managers and stakeholders to meet aggressive project timelines.
Utilize industry-standard EDA tools (Cadence Virtuoso) and scripting (Skill, Python, etc.) to automate and optimize layout tasks and verification flows.

What We're Looking For

Education: BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or related fields.
4+ years of experience in AMS Layout Design.
Hands-on Layout Experience in high-speed SERDES architectures
Hand-on Layout Experience in Advanced FinFET technology nodes
You should be highly skilled in the following areas:
Cadence Virtuoso and SKILL
AMS Layout Verification flows (DRC, LVS, EMIR) and chip assembly techniques
Working closely with AMS Design Engineers to ensure the intent of design is built in Layout
Excellent communication skills are necessary to work with multiple domain experts, such as digital/VLSI, Photonics, and packaging.

Additional Compensation And Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Staff Analog Layout Engineer