automation, Ovm, Tcl Scripting, Verilog, Perl, HVL, GLS, Uvm, RTL, SV, Specman, SDF sim debug, test-bench development, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

automation, Ovm, Tcl Scripting, Verilog, Perl, Uvm, GLS, RTL, SV, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification