Perl, Verilog, Computer Architecture, Oops Concepts, Python, VMM, UVM methodology, constrained random verification, systemverilog, functional coverage

Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

Axi, APB, RISC-V, Uvm, Microarchitecture-level verification, AHB, Processor Architecture