System Verilog, HBM4, Assertion-based verification, Cadence Xcelium, Power-aware verification, silicon debug, Crypto Network-on-Chip NoC, Formal-based verification, DRAM Memory Controller IPs, Gate-level simulation, Uvm, Synopsys VCS, Asic Design Verification, Synopsys JasperGold, Verification management tools, VC Formal, LPDDR6

System Verilog, Assertion-based verification, Verification methodologies, Power-aware verification, Verification management tools, silicon debug, Gate-level simulation, Uvm, formal verification

Sta, RTL2GDS, EDA Tools, Timing Analysis, Physical Design