Verilog, System Verilog, LPDDR, Uvm, DDR memory protocols, HBM, Functional Verification

Verilog, System Verilog, Functional Verification, LPDDR, Uvm, DDR memory protocols, HBM

Dft, DFX, Verification flows, Analog Patterns flow, SPyglass flows, DFX Architecture, Top Level Integration, Digital Design

static timing analysis, low-power design methodologies, micro-architecture development, Cadence-based ASIC design environments, SystemVerilog RTL design, Lint CDC formal verification, DFT including scan testability, Logic Synthesis

Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification

Python, Static timing analysis, Unix, Splunk, AI ML, Linux, Lsf, Bitbucket, Jenkins, Git, make, EDA Tools, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, DesignSync, Dft, Design revision control, Power-aware flows