automation, Ovm, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, Specman, SDF sim debug, test-bench development, HVL, closure constraint randomization, functional and code coverages, assertions development, eRM methodology, formal verification

System Verilog, Pcie, Uvm, PXC, CXL, RTL Design using Verilog