Tcl, Makefile, static timing analysis, python, Perl, ASIC design flow, EM IR crosstalk analysis, Dfm, Physical Verification, Innovus, Tempus, Cadence EDA tools, hierarchical physical design strategies, low power design, Voltus, formal verification, Tk, Dft, Genus

telemetry , Python, Analog Mixed-Signal Design, Stability Compensation, Precision Circuits, Advanced CMOS Processes, Monte Carlo Aging, Spectre, Noise PSRR, Cadence Virtuoso, PVT Mismatch Corners, Variation Reliability

Pvs, Tcl, Python, Perl, Awk, Calibre, ICV