clocking , Arm, Trace32, Multimedia, Microprocessors, Computer Architecture, interconnect safety, Synthesis, Security, ARM Debug, Ace, RTL design flow, Verilog RTL coding, RISC-V, APB, Axi, Reset, ATB, BUS Protocols, Chip Assembly, LINT, RTL signoff tools, Serial Interfaces, cdc, ARM CoreSight ETM, IP Integration, Arm Cortex-M A R processor-based SoC debug infrastructure, External Bus Interfaces, RDC, System modes

System Verilog, Environment Development, Uvm, Design Verification, Functional Verification, Test Plan Generation

layout and physical verification, jitter and signal equalization techniques, Cadence tool experience, Phase Interpolator, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA

routing, RTL-to-GDS flows, Rtl Design, floorplanning, Physical Verification methodologies, Cadence, LVS, Physical Design, EDA Tools, ERC, Timing Closure, DRC, Placement, Synopsys, Siemens tools, Clock Tree Synthesis

Analog IC design, IC layout, Design Verification