C, Python, Perl, MATLAB, Parasitic Extraction, High-speed SerDes circuits, systemverilog, Mixed-signal verification, Verilog-A, Cadence Virtuoso, RF ADE, Spectre

display , simulations , Usb, Pcie, Timing Constraints, UCIe, Verilog Coding, LINT, RTL checks, data path designs, cdc, Rtl Design, Verilog testbench, MIPI, synthesis flow, SDC, HDMI, DPHY

routing, RTL-to-GDS flows, Rtl Design, floorplanning, Physical Verification methodologies, Cadence, LVS, Physical Design, EDA Tools, ERC, Timing Closure, DRC, Placement, Synopsys, Siemens tools, Clock Tree Synthesis

Verilog, Tcl, Ethernet, Perl, C, Scripting Languages, Pcie, AHB, Flash interfaces, RDC constructs, IP Synthesis, IP development flow, QuadSPI, FPGA Emulation Board, Axi, SERDES, BUS Protocols, HDLs, DDR4, High Speed Serial protocols, ATPG, cdc, AMBA, Testplan development, VHDL, microcontroller architecture, pre silicon validation, LPDDR4, Dft